Samsung Electronics has unveiled a next-generation 3D memory architecture that directly stacks high-bandwidth memory (HBM) on AI accelerators. This new approach moves away from the traditional horizontal layout of HBM, aiming to reduce data transfer distances and power consumption while providing integrated design and packaging for AI semiconductors.
At the 'FMS 2026' event held from August 4 to 6 in Santa Clara, California, Samsung introduced its next-generation 3D memory, 'zHBM,' and a mock-up of 'zNAND-O.' The company also showcased its 10th generation V-NAND, 'V10 BV-NAND,' which features over 400 layers.
Unlike the previous structure that placed HBM beside AI accelerators, zHBM employs a vertical stacking method above the accelerator. This design focuses on reducing the distance for data transfer between the processing unit and memory, enhancing bandwidth and power efficiency.
According to Samsung, systems based on zHBM can achieve up to eight times the performance of HBM5. The power efficiency is expected to improve by up to three times, while thermal resistance is projected to be reduced by more than half.
An interlayer that allows for customized functionalities will be implemented between the accelerator and memory. This will enable adjustments to memory capacity, processing capabilities, and data handling structures tailored to the AI processors developed by clients.
However, the products unveiled are mock-ups and not yet in mass production. The commercialization schedule will likely be determined after joint design efforts and thermal management technology validation with clients.
In NAND flash technology, Samsung has also expanded vertical stacking capabilities. The zNAND-O combines V-NAND technology with silicon through vias, allowing NAND chips to be packaged in 4 or 8 layers. This innovation is expected to enhance data loading speeds and space efficiency in on-device AI environments for smartphones and PCs.
Samsung also presented its V10 BV-NAND, which features over 400 layers. This technology utilizes a bonding method that vertically joins wafers after separately creating cells and peripheral circuits, resulting in a 58% increase in data storage capacity within the same area compared to the previous generation. Improvements in read, write, and input/output performance are also planned to meet the demands of high-capacity storage solutions for AI data centers.
Kioxia announced its plans for developing 10th generation BiCS flash with over 400 layers in June, indicating that the NAND competition will focus on increasing integration while reducing power consumption and production costs.
At the event, Samsung also showcased HBM4E, HBM5, and LPDDR5X-PIM, which performs some computations within the memory. The company aims to address the storage needs for AI training and inference with its enterprise SSDs, PM1763 and high-capacity product BM1773.
This technology reveal signifies Samsung's strategy to expand its business scope by designing semiconductor system architectures alongside memory product performance. As the integration of AI accelerators and memory strengthens, the impact of foundry, logic design, and advanced packaging capabilities on competitive bidding is expected to grow.
Samsung plans to leverage its integrated structure of memory, system semiconductor design, foundry, and packaging to support clients from the product design phase through to mass production. Successfully applying next-generation 3D memory to customer products will depend on effectively managing yield, heat generation, and packaging costs.
* This article has been translated by AI.
Copyright ⓒ Aju Press All rights reserved.