Huawei, a major Chinese IT company, has announced that it has resolved the critical heat issue identified in its 'Law of Tao' presented in May.
Due to U.S. sanctions preventing the import of essential semiconductor manufacturing equipment like EUV (extreme ultraviolet) lithography machines, Huawei has stated its vision to produce 1.4nm performance semiconductors within five years using the Law of Tao. This law aims to increase chip density by applying logic folding design without reducing circuit line width. However, concerns were raised that this design could lead to heat generation issues.
He Tingbo, president of Huawei's semiconductor division, posted a revised paper related to the Law of Tao on the ChinaXiv preprint platform under the Chinese Academy of Sciences on September 4, as reported by Shanghai Securities News on the 7th. He had previously published the first paper on May 25 and a second revised version in July, marking this as the third revision within four months.
The paper focuses on the impact of logic folding technology on chip power consumption and heat generation, presenting empirical data from the 'Kirin 2026' chip. Conventional wisdom suggests that stacking more active transistors vertically increases power density, leading to greater heat burden. However, the paper indicates that the test results for Kirin 2026 show that an increase in transistor density does not necessarily correlate with higher power consumption.
According to the paper, the Kirin 2026 features a 55% increase in transistor density, yet power consumption for the neural processing unit (NPU), graphics processing unit (GPU), and central processing unit (CPU) performance cores decreased by 66%, 58%, and 41%, respectively, under the same performance conditions.
He explained that most of the chip's energy consumption occurs not during the computational processes of the transistors but during the transmission of data and signals within the chip. Logic folding reduces the signal transmission path by converting long horizontal wiring into shorter vertical connections, thereby lowering interconnect capacitance and energy consumption. However, the paper also notes that the adoption of logic folding does not guarantee low power consumption.
The first chip to utilize Huawei's logic folding technology is the Kirin 2026. This chip applies logic folding by expanding the traditional 2D logic design into a two-layer structure. The Kirin 2026 is expected to be featured in Huawei's flagship Mate 90 series smartphones, set to launch this fall. Although the Kirin 2026 is manufactured using a 7nm process, there are predictions that its performance will rival that of 3nm chips.
* This article has been translated by AI.
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